 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| never stop thinking. data sheet, rev. 1.21, nov. 2005 communications ADM6993F/fx fiber to fast ethernet converter (ts1000 cpe complied)
edition 2005-11-28 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. template: template_a4_3.0.fm / 3 / 2005-01-17 trademarks abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10 bases?, easyport?, vdslite? are trademarks of infi neon technologies ag. microsoft ? is a registered trademark of microsoft corporation, linux ? of linus torvalds, visio ? of visio corporation, and framemaker ? of adobe systems incorporated. fiber to fast ethernet converter (ts1000 cpe complied) ADM6993F/fx revision history: 2005-11-28, rev. 1.21 previous version: page/date subjects (major change s since last revision) 2003-03-05 rev.1.0: first release of ADM6993F 2003-07-02 rev. 1.1: added section 4.2 2003-10-06 rev. 1.2: updated section 2. 2.5, 4.2.5, 4.2.12 & 4.2.13 2005-09-09 changed to the new infineon format 2005-09-09 rev. 1.2 changed to rev. 1.21 2005-11-28 minor change. included green package information data sheet 4 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 data lengths conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 pin type and buffer type abbreviation s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 oam engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 10/100m phy block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 auto negotiation and speed configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 auto negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 speed configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 switch functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.2 address learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.3 address recognition and packet forwardi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.4 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.5 buffers and queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.6 back off algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.7 inter-packet gap (ipg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.8 illegal frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.9 half duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.10 full duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.11 broadcast storm filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.12 auto tp mdix function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 converter functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.1 fault propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.2 redundant link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.3 loop-back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.4 snooping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.5 fiber_sd led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6 serial management interface (smi) register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.1 preamble suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6.2 read eeprom register via smi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6.3 write eeprom register via sm i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.7 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.7.1 write eeprom register via eeprom interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 eeprom register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table of contents data sheet 5 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet table of contents 4.2.1 eeprom register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.1 dc characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2 ac characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 data sheet 6 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet list of figures figure 1 ADM6993F/fx block diagram 9 figure 2 ADM6993F/fx pin assignment 10 figure 3 smi read operation 29 figure 4 smi write operation 29 figure 5 power on reset timing 54 figure 6 eeprom interface timing 54 figure 7 10base-tx mii input timing 55 figure 8 10base-tx mii output timing 56 figure 9 100base-tx mii input timing 56 figure 10 100base-tx mii output timing 57 figure 11 reduce mii timing 58 figure 12 gpsi (7-wire) input timing 59 figure 13 gpsi (7-wire) output timing 59 figure 14 smi timing 60 figure 15 128 pqfp packaging for ADM6993F/fx 61 list of figures data sheet 7 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet list of tables table 1 data lengths conventions 9 table 2 ADM6993F/fx abbreviations for pin type 11 table 3 abbreviations for buffer type 11 table 4 port 0/1 twisted pair interface (8 pins) 12 table 5 port 2 (mii/rmii/gpsi) interface (17 pins) 12 table 6 port 1 alternative mii port interface (17 pins) 14 table 7 led interface (13 pins) 15 table 8 eeprom interface (4 pins) 17 table 9 configuration interface (28 pins) 18 table 10 ground/power interface (27 pins) 20 table 11 miscellaneous (14 pins) 21 table 12 speed configuration 24 table 13 port rising/falling threshold 26 table 14 drop scheme for each queue 27 table 15 smi read/write command format 28 table 16 eeprom register map 31 table 17 registers address spaceregisters address space 33 table 18 registers overview 33 table 19 register access types 34 table 20 registers clock domainsregisters clock domains 35 table 21 other filter regsiters 45 table 22 other tag port rule 0 registers 49 table 23 other tag port rule 1 regsiters 50 table 24 electrical absolute maximum rating 53 table 25 recommended operating conditions 53 table 26 dc electrical characteri stics for 3.3 v operation 53 table 27 power on reset timing 54 table 28 eeprom interface timing 54 table 29 10base-tx mii input timing 55 table 30 10base-tx mii output timing 56 table 31 100base-tx mii input timing 57 table 32 100base-tx mii output timing 57 table 33 100base-tx mii output timing 58 table 34 gpsi (7-wire) input timing 59 table 35 gpsi (7-wire) output timing 60 table 36 smi timing 60 list of tables ADM6993F/fx data sheet product overview data sheet 8 rev. 1.21, 2005-11-28 1 product overview features and the block diagram. 1.1 overview the ADM6993F/fx is a single chip integrating two 10/100 mbps mdix tx/fx transceivers, a three-port 10/100m ethernet l2 switch controller, and one oam engine to meet demanding applications, including fiber-to-ethernet media converters, especially the fiber to the home (ftth) media converters. the ADM6993F/fx feature set includes link pass through (lpt), ts1000 oam frame rece iving/processing/transmitting, programmable link status led display, various loop-back modes, and one configur able mii ports for snooping/inserting oam frame from/to 100fx. the ADM6993Fx is the environment ally friendly ?green? package version. the ADM6993F/fx supports priority features on port-bas e priority, vlan tag priority and ip tos precedence checking at individual ports. this is done through a small low-cost micro controller to initialize or on-the-fly to configure. the priority of packets can be tagged base d on tcp port number for the multi-media application. the 2 nd mac interface could be selected as tp/fx or mii/rmii/gpsi to connect with bridge devices for different media. the 3 rd mac interface could be selected as mii/rmii/gpsi to connect wit h routing devices, and bridge devices for different media on the media side of port0/1, the ADM6993F/fx suppor ts auto mdix 10base-t/100base-tx and 100base-fx as specified by the ieee 802.3 committee through uses of digital circuitry and high speed a/d. ADM6993F/fx supports serial management interface (smi) for a small low-cost micro controller to initialize or configure. it also provides port status for remo te agent monitor and smart counter for port statistics. 1.2 features main features: ? 3-port10/100m switch integrated with a 2-port phy (10/100tx and 100fx) and 3 rd mac port as gpsi/mii/rmii ? embedded oam engine complying with ts1000 ? provides tx<-->fx converter modes with link pass through (lpt) ? configurables mii ports for snooping/inserting oam frame from/to fiber phy ? built-in data buffer 6kx64bit sram ? up to 2k mac unicast addresses with a 4-way associative hashing table ? mac address learning table with aging function ? two queues per port for qos purposes ? port-base, 802.1p and tcp/ip tos priority ? store & forward architecture ? forwarding and filtering at non-blocking full wire speed ? 802.3x flow control for full duplex and back-pressure for half duplex ? supports auto-negotiation ? packet lengths up to 1536 bytes. ? broadcast storming filter ? port-base vlan/tag-base vlan ? 16 entries of packet classification and marking or filt ering for tcp/udp port numbering, ip protocol id and ethernet type ? serial management interface for low-end cpus ? provides port status for remote agent monitoring ? provides smart counters fo r port statistics reporting ? 128 pqfp packaging with 2.5 v/3.3 v power supply data sheet 9 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet product overview 1.3 block diagram figure 1 ADM6993F/fx block diagram 1.4 data lengths conventions table 1 data lengths conventions qword 64 bits dword 32 bits word 16 bits byte 8 bits nibble 4 bits port1 mac port2 mac port0 mac dma learn dma learn dma learn packet buffer address filtering buffer management switch fabric link list link list buffer address filtering buffer eeprom interface smi interface led display rcv clkgen rstgen cenctrl mux port1 tx/fx phy port0 tx/fx phy mux mii rmii gpsi mii rmii gpsi oam processor ADM6993F/fx data sheet interface de scription data sheet 10 rev. 1.21, 2005-11-28 2 interface description this chapter describes pin diagram , pin type and buffer type abbreviations, and pin descriptions. 2.1 pin diagram figure 2 ADM6993F/fx pin assignment lpt_dis chip_dis cas_dis lpbk_p0 lpbk_p1 lpbk_p2 p2linkf p2spdten p2dphalf p2col p2crs vcc2ik p2txclk gndik p2txen p2txd0 p2txd1 p2txd2 p2txd3 p1rxd3 p1rxd2 p1rxd1 p1rxd0 vcc3o ck25mo gndo sfield_15 sfield_14 sfield_13 sfield_12 sfield_11 mc_failure insert pd_detect p0_mdi xoven scan_en scan_md led_link1 led_full0 led_full1 led_lpbk led_wan_fail int_n eedo eedi vcc2ik vcc2ik eesk eecs gndik sdc sdio p0_andis p0_rechalf p0_rec10 p0_fcdis ftpr_mode0 ftpr_mode1 p1_andis p1_rechalf p1_rec10 p1_fcdis rc xi xo bypass_pause ledmode2 nc vccpll gndpll control vref gndbias rtx vccrg vcca2(2.5) txp0 txn0 gndr rxp0 rxn0 vccad(3.3) rxn1 rxp1 gndt txn1 txp1 vcca2(2.5) gndik p1txd3 p1txd2 p1txd1 p1txd0 vcc2ik p1txclk p1txen p1rxdv p1rxclk test p2_fcdis gndik p2rxclk p2rxdv p2rxd0 p2rxd1 p2rxd2 p2rxd3 gndik gndik p1col p1crs lnkact0/led_data0 lnkact1/led_data1 vcc2ik vcc2ik p1linkf gndo gndo p1spdten p1dphalf ldspd0 ldspd1/led_fiber_sd dupcol0/led_col0 dupcol1/led_col1 vcc3o vcc3o led_link0 ADM6993F 34 33 32 31 24 23 22 21 15 17 18 19 20 35 36 37 38 14 13 16 25 26 27 28 29 30 2 1 6 4 5 3 7 8 9 10 11 12 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 96 95 94 93 92 97 98 99 100 101 102 68 69 70 71 72 73 74 75 76 65 66 67 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 39 40 41 42 43 44 45 46 47 4 8 49 126 112 113 114 115 116 117 118 119 120 121 122 123 124 125 111 110 109 108 107 106 105 104 103 127 128 data sheet 11 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet interface de scription 2.2 pin type and buffer type abbreviations standardized abbreviations: table 2 ADM6993F/fx abbreviations for pin type abbreviations description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. ao output. analog levels. ai/o input or output. analog levels. pwr power gnd ground mcl must be connected to low (jedec standard) mch must be connected to high (jedec standard) nu not usable (jedec standard) nc not connected (jedec standard) table 3 abbreviations for buffer type abbreviations description z high impedance pu1 pull up, 10 k ? pd1 pull down, 10 k ? pd2 pull down, 20 k ? ts tristate capability: the corres ponding pin has 3 operationa l states: low, high and high- impedance. od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to shar e as a wire-or. an external pull-up is required to sustain the inactive state until another agent drives it, and must be provid ed by the central resource. oc open collector pp push-pull. the corresponding pin has 2 operational states: active-low and active-high (identical to output with no type attribute). od/pp open-drain or push-pull. the corresponding pin can be configured either as an output with the od attribute or as an output with the pp attribute. st schmitt-trigger characteristics ttl ttl characteristics ADM6993F/fx data sheet interface de scription data sheet 12 rev. 1.21, 2005-11-28 2.3 pin descriptions ADM6993F/fx pins are categorized into one of the following groups: ? port 0/1 twisted pair interface, 8 pins ? port 2 (mii/rmii/gpsi) interface, 17 pins ? port 1 alternative mii port interface, 17 pins ? led interface, 13 pins ? eeprom interface, 4 pins ? configuration interface, 28 pins ? ground/power interface, 27 pins ? miscellaneous, 14 pins note: if not specified, all signals default to digital signals. table 4 port 0/1 twisted pair interface (8 pins) pin or ball no. name pin type buffer type function 40 txp_0 ao twisted pair transmit output positive. 50 txp_1 ao 41 txn_0 ao twisted pair transmit output negative. 49 txn_1 ao 43 rxp_0 ai twisted pair receive input positive. 47 rxp_1 ai 44 rxn_0 ai twisted pair receive input negative. 46 rxn_1 ai table 5 port 2 (mii/rmii/gpsi) interface (17 pins) pin or ball no. name pin type buffer type function 87 p2txd0 i/o ttl, pd, 8ma port 2 mii transmit data bit 0 synchronous to the rising edge of txclk. fxmode0 fxmode0 during power on reset, value will be latched by ADM6993F/fx at the rising e dge of resetl as bit 0 of fxmode. 86 p2txd1 i/o ttl, pd, 8ma port 2 mii transmit data bit 1 synchronous to the rising edge of txclk. fxmode1 fxmode1 during power on reset, value will be latched by ADM6993F/fx at the rising e dge of resetl as bit 1 of fxmode. fxmode [1:0] interface 00 b , both port0 & port1 are tp port 01 b , port0 is tp port and port1 is fx port 10 b , port0 is tp port and port1 is fx port (converter mode) 11 b , both port0 & port1 are fx port data sheet 13 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet interface de scription 85 p2txd2 i/o ttl, pd, 8ma port 2 mii transmit data bit 2 synchronous to the rising edge of txclk. p2busmd0 p2busmd0 during power on reset, value will be latched by ADM6993F/fx at the risi ng edge of resetl as p2busmd0. 84 p2txd3 i/o pd, 8ma port 2 mii transmit data bit 3 p2busmd1 p2busmd1 during power on reset, value will be latched by ADM6993F/fx at the risi ng edge of resetl as p2busmd1. busmd[1:0] interface 00 b , mii(default) 01 b , rmii 10 b , gpsi 88 p2txen i/o pd, 8ma port 2 mii transmit enable synchronous to the rising edge of txclk disbp disbp. disable back pressure 0 b , enable back-pressure(default) 1 b , disable back-pressure 108, 107, 106, 105 p2rxd[3:0] i ttl, pd port 2 mii receive data bit 3 ~ 0 104 p2rxdv i ttl, pd port 2 mii receive data valid 93 p2col i ttl, pd port 2 mii collision input 92 p2crs i ttl, pd port 2 mii carrier sense 103 p2rxclk i ttl, pd port 2 mii receive clock input 90 p2txclk i ttl, pd port 2 mii transmit clock input 96 p2linkf i ttl, pu p2linkf this pin will be used to inpu t the link stat us of port2 1 b , link fail 95 p2spdten i ttl, pd p2spdten this pin will be used as po rt 2 speed status input 1 b , 10m 94 p2dphalf i ttl, pd p2dphalf this pin will be used as port 2 duplex status input 1 b , half duplex table 5 port 2 (mii/rmii/g psi) interface (17 pins) (cont?d) pin or ball no. name pin type buffer type function ADM6993F/fx data sheet interface de scription data sheet 14 rev. 1.21, 2005-11-28 table 6 port 1 alternative mii po rt interface (17 pins) pin or ball no. name pin type buffer type function 56 p1txd0 (pcs_p1rxd0) /chipid[0] i/o ttl, pd, 8ma port 1 mii transmit data bit 0/chip id bit 0 during power on reset, value will be latched by ADM6993F/fx at the risi ng edge of resetl as chipid[0]. this pin will become pcs_p1rx d0 if p1busmd[1:0] is 11. synchronous to the rising edge of txclk. 55 p1txd1 (pcs_p1rxd1) /chipid[1] i/o ttl, pd, 8ma port 1 mii transmit data bit 1/chip id bit 1 during power on reset, value will be latched by ADM6993F/fx at the risi ng edge of resetl as chipid[1]. this pin will become pcs_p1rx d1 if p1busmd[1:0] is 11. synchronous to the rising edge of txclk. 54 p1txd2 (pcs_p1rxd2) /p1busmd0 i/o ttl, pu, 8ma port 1 mii transmit data bit 2/ port 1 bus mode bit 0 during power on reset, value will be latched by ADM6993F/fx at the risi ng edge of resetl as p1busmd0. this pin will become pcs_p1rx d2 if p1busmd[1:0] is 11. synchronous to the rising edge of txclk. p1busmd[1:0] interface 00 b , mii (power down tx phy) 01 b , rmii (power down tx phy) 10 b , gpsi (power down tx phy) 11 b , tp/fx (default) 53 p1txd3 (pcs_p1rxd3) /p1busmd1 i/o ttl, pu, 8ma port 1 mii transmit data bit 3/ port 1 bus mode bit 1 during power on reset, value will be latched by ADM6993F/fx at the risi ng edge of resetl as p1busmd1. this pin will become pcs_p1rx d3 if p1busmd[1:0] is 11. synchronous to the rising edge of txclk. p1busmd[1:0] interface 00 b , mii (power down tx phy) 01 b , rmii (power down tx phy) 10 b , gpsi (power down tx phy) 11 b , tp/fx (default) 59 p1txen (pcs_p1rxdv) i/o ttl, pd, 8ma port 1 mii transmit enable this pin will become pcs_p1rxdv if p1busmd[1:0] is 11. synchronous to the rising edge of txclk 83, 82, 81, 80 p1rxd[3:0] (pcs_p1txd[3: 0]) i ttl, pd port 1 mii receive data bit 3 ~ 0 these pins will become pcs_p1txd[3:0] if p1busmd[1:0] is 11 60 p1rxdv (pcs_p1txen) i ttl, pd port 1 mii receive data valid this pin will become pcs_p1t xen if p1busmd[1:0] is 11 111 p1col (pcs_p1col) i/o ttl, pd port 1 mii collision input this pin will become pcs_p1col if p1busmd[1:0] is 11 and becomes an output pin data sheet 15 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet interface de scription 112 p1crs (pcs_p1crs) i/o ttl, pd port 1 mii carrier sense this pin will become pcs_p1crs if p1busmd[1:0] is 11 and becomes an output pin 61 p1rxclk (pcs_p1rxclk ) i/o ttl, pd port 1 mii receive clock input this pin will become pcs_p1crs if p1busmd[1:0] is 11 and becomes an output pin 58 p1txclk (pcs_p1txclk ) i/o ttl, pd port 1 mii transmit clock input this pin will become pcs_p1crs if p1busmd[1:0] is 11 and becomes an output pin. 117 p1linkf i ttl, pu port 1 link fail status this pin will be used to input th e link status of port1 if port1 is not connected to internal phy 1 b , link fail 120 p1spdten i ttl, pd port 1 speed status this pin will be used as port 1 speed status input if port1 is not connected to internal phy 1 b , 10m 121 p1dphalf i ttl, pd port 1 duplex status this pin will be used as port 2 duplex status input if port1 is not connected to internal phy 1 b , half duplex table 7 led interface (13 pins) pin or ball no. name pin type buffer type function 113 lnkact_0 i/o ttl pd 8ma port0 link & active led/link led. if ledmode_0 is 1, this pin indicates both link status and rx/tx activity. when link status is link_up, lnkact_0 will be turned on. while port0 is receiving /transmitting data, lnkact_0 will be off for 100ms and then on for 100ms. if ledmode_0 is 0, this pin only indicates rx/tx activity. led_data_0 port0 led data ledmode_0 led mode for link/act led of port0. during power on rese t, value will be latche d by ADM6993F/fx at the rising edge of resetl as ledmode_0. table 6 port 1 alternative mii port interface (17 pins) (cont?d) pin or ball no. name pin type buffer type function ADM6993F/fx data sheet interface de scription data sheet 16 rev. 1.21, 2005-11-28 114 lnkact_1 i/o ttl pd 8ma port1 link & active led/link led. if ledmode_2 is 1, this pin indicates both link status and rx/tx activity. when link status is link_up, lnkact_1 will be turned on. while port1 is receiving /transmitting data, lnkact_1 will be off for 100ms and then on for 100ms. if ledmode_2 is 0, this pin only indicates rx/tx activity. led_data_1 port1 led data ledmode_1 led mode duplex/col led of port0 & port1. during power on rese t, value will be latche d by ADM6993F/fx at the rising edge of resetl as ledmode_1. if ledmode_1 is 1, dupcol[1:0] will display both duplex condition and collision status. if ledmode[1] is 0, only collision status will be displayed. 30 ledmode_2 i ttl pd led mode for link/act led of port1 0 b , act 1 b , link/act 124 dupcol_0 i/o ttl pd 8ma port0 duplex led if ledmode_1 is 1, this pin indicates both duplex condition and collision status. when full_dupl ex, this pin will be turned on for port0. when half_duplex and no collision occurs, this pin will be turned off. when half_duplex and a collision occurs, this pin will be off fo r 100ms and then on for 100ms. if ledmode_1 is 0, this pin in dicates collision status. when in half_duplex and a collision occurs, this pin will be off for 100ms and turns on for 100ms. led_col_0 port0 collision led dis_learn disable address learning. during power on rese t, value will be latche d by ADM6993F/fx at the rising edge of resetl as di s_learn. if dis_learn is 1, mac address learning will be disabled. 125 dupcol_1 i/o ttl pu 8ma port1 duplex if ledmode_1 is 1, this pin indicates both duplex condition and collision status. when full_dupl ex, this pin will be turned on for port1. when half_duplex and no collision occurs, this pin will be turned off. when half_duplex and a collision occurs, this pin will be off for 100ms and then on for 100ms. if ledmode_1 is 0, this pin in dicates collision status. when half_duplex and a collision occurs, this pin will be off for 100ms and turns on for 100ms. led_col_1 port1 collision led en_oam enable internal oam frame processor. during power on rese t, value will be latche d by ADM6993F/fx at the rising edge of resetl as en_oam. if en_o am is 0, the internal oam engine will be disabled. table 7 led interface (13 pins) (cont?d) pin or ball no. name pin type buffer type function data sheet 17 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet interface de scription 122 ldspd_0 i/o ttl pu 8ma port0 speed led used to indicate speed status of port0. when operating in 100mbps this pin is turned on, and when operating in 10mbps this pin is off. rdnt_en enable redundant capability during power on rese t, value will be latche d by ADM6993F/fx at the rising edge of resetl as rdnt_en. if rdnt_en is 0, "redundant" capability will be disabled. for ts1000 application this pin should have a value of 0. 123 ldspd_1 i/o ttl pu 8ma port1 speed led used to indicate speed status of port1. when operating in 100mbps this pin is turned on, and when operating in 10mbps this pin is off. led_fiber_sd led_fiber_sd used to indicate signal status of port1 when ADM6993F/fx is operating in converter mode. snp_en enable snooping mode during power on rese t, value will be latche d by ADM6993F/fx at the rising edge of resetl as snp_en. if snp_en is 0, ?snooping? capability will be disabled. 1, 128 led_link[1:0] o ttl 8ma port[1:0] link led these pins indicate link status. when link status is link_up, these pins will be turned on for relevant port. 3, 2 led_full[1:0] o ttl 8ma port[1:0] full duplex led these pins indicate current duplex condition of port0. when full_duplex, these pins will be turned on for relevant port. when half_duplex these pins will be turned off for relevant port. 4 led_lpbk i/o ttl 8ma loop back test led while performing loop back test this pin is turned on. 5 led_wan_fail o ttl 8ma wan fail led when receiving an oam frame which has a s2 bit = 1, this pin is turned on. table 8 eeprom interface (4 pins) pin or ball no. name pin type buffer type function 7 eedo i ttl pu eeprom data output serial data input fr om eeprom. this pin is internal pull-up. 12 eecs/ifsel i/o pd 4ma eeprom chip select this pin is active high chip enabled for eeprom. when resetl is low, it will be tristate. table 7 led interface (13 pins) (cont?d) pin or ball no. name pin type buffer type function ADM6993F/fx data sheet interface de scription data sheet 18 rev. 1.21, 2005-11-28 11 eeck/sdc i/o ttl pu 4ma serial clock this pin is the eeprom clock source. when resetl is low, it will be tristate. this pin is internal pull-up. 8 eedi i/o ttl pu 4ma eeprom serial data input this pin is the output for serial data transfer. when resetl is low, it will be tristate. table 9 configuration interface (28 pins) pin or ball no. name pin type buffer type function 16 p0_andis i ttl pd auto-negotiation disable for port0 0 b e , enable 1 b d , disable p0_forcemd p0_forcemd if eeprom register 6[8] is 1, this pin will be used to enable/disable port0 emulated force mode 0 b e , enable 1 b d , disable 17 p0_rechalf i ttl pd recommend half duplex communication for port0 0 b f , full 1 b h , half 18 p0_rec10 i ttl pd recommend 10m for port0 0 b 100 , 100m 1 b 10 , 10m 19 p0_fcdis i ttl pd flow control disable for port0 0 b e , enable 1 b d , disable 22 p1_andis i ttl pd auto-negotiation disable for port1 0 b e , enable 1 b d , disable 23 p1_rechalf i ttl pd recommend half duplex communication for port1 0 b f , full 1 b h , half 24 p1_rec10 i ttl pd recommend 10m for port1 0 b 100 , 100m 1 b 10 , 10m 25 p1_fcdis i ttl pd flow control disable for port1 0 b e , enable 1 b d , disable 63 p2_fcdis i ttl pd flow control disable for port2 0 b e , enable 1 b d , disable table 8 eeprom interface (4 pins) (cont?d) pin or ball no. name pin type buffer type function data sheet 19 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet interface de scription 67 xoven i ttl pd auto-mdix enable. 0 b d , disable 1 b e , enable 68 p0_mdi i ttl pu mdi/mdix control for port0 this setting will be ignor ed if enable auto-mdix. 0 b mdix , mdix 1 b mdi , mdi 21, 20 ftpr_mode[1: 0 i ttl pd fault propagation mode / link pass through 00 b , fx fail -> utp fail, utp fail -> fx transmit oam frame 01 b , fx fail -> utp fail, utp fail -> fx transmit fefi 10 b r , reserved 11 b d , disable 99 lpbk_p0 i ttl pd enable loop back test for port0 0 b d , disable 1 b e , enable 98 lpbk_p1 i ttl pd enable loop back test for port1 0 b d , disable 1 b e , enable 97 lpbk_p2 i ttl pd enable loop back test for port2 0 b d , disable 1 b e , enable 69 pd_detect i ttl pd power failure detected 0 b n , normal 1 b tx , ADM6993F/fx will transmit an oam frame to indicate power failure. 70 insert i ttl pd isolate tx portion of internal oa m engine to insert any frame from mii interface of port1 0 b d , disable 1 b e , enable 71 mc_failure i ttl pd media converter (mc) failure detected 0 b n , normal 1 b tx , ADM6993F/fx will transmit an oam frame to indicate mc failure. 72 sfield_11 i ttl pd bit 11 value of s field in transmitted oam frame 73 sfield_12 i ttl pd bit 12 value of s field in transmitted oam frame 74 sfield_13 i ttl pd bit 13 value of s field in transmitted oam frame 75 sfield_14 i ttl pd bit 14 value of s field in transmitted oam frame 76 sfield_15 i ttl pd bit 15 value of s field in transmitted oam frame table 9 configuration interface (28 pins) (cont?d) pin or ball no. name pin type buffer type function ADM6993F/fx data sheet interface de scription data sheet 20 rev. 1.21, 2005-11-28 101 chip_dis i ttl pd chip disable 0 b d , disable 1 b e , enable 100 cas_dis o ttl 4ma disable cascaded chip 0 b d , disable 1 b e , enable 102 lpt_dis i ttl pd link pass through disable 0 b e , enable 1 b d , disable 29 bypass_paus e i ttl pd bypass frame the destination address is reserved ieee mac address 0 b d , disable 1 b e , enable table 10 ground/power interface (27 pins) pin or ball no. name pin type buffer type function 42, 48 gndtr gnd, a ground used by ad receiver/transmitter block. 39, 51 vcca2 pwr, a 2.5 v used for analogue block 45 vccad pwr, a 3.3 v used for tx line driver 36 gndbias gnd, a ground used by digital substrate 38 vccbias pwr, a 3.3 v used for bios block 33 gndpll gnd, a ground used by pll 32 vccpll pwr, a 2.5 v used for pll 13, 52, 64, 89, 109, 110 gndik gnd, d ground used by digital core and pre-driver 9, 10, 57, 91, 115, 116 vccik pwr, d 2.5 v used for digital core and pre-driver 77, 118, 119 gndo gnd, d ground used by digital pad 79, 126, 127 vcc3o pwr, d 3.3 v used for digital pad. table 9 configuration interface (28 pins) (cont?d) pin or ball no. name pin type buffer type function data sheet 21 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet interface de scription table 11 miscellaneous (14 pins) pin or ball no. name pin type buffer type function 6 int# o ttl od 4ma interrupt this pin will be used to interrupt external management device. this is a low active and open drain pin. 15 sdio i/o ttl pu 8ma serial management data this pin is in/out to phy. wh en resetl is low, this pin will be tristate. 14 sdc i ttl 8ma serial manageme nt data clock 78 cko25m o ttl pu 8ma 50m output for rmii and 25m clock output for others 34 control ao fet control signal the pin is used to control fet for 3.3 v to 2.5 v regulator. 37 rtx a tx resistor 35 vref a analog power failure detected 26 rc i ttl st rc input for power on reset ADM6993F/fx sample pin rc as resetl with the clock input from pin xi. 27 xi ai 25m crystal input 25m crystal input. variation is limited to +/- 50ppm. 28 xo ao 25m crystal output when connected to oscillator, th is pin should left unconnected. 31, 62, 65, 66 nc no connection ADM6993F/fx data sheet function description data sheet 22 rev. 1.21, 2005-11-28 3 function description the ADM6993F/fx integrates a two 100b ase-x physical layer device (phy), two complete 10baset modules, a three-port 10/100 switch controller and memory into a sing le chip for both 10mbps and 100 mbps ethernet switch operations. it also supports 100base-fx operations thro ugh external fiber-optic tr ansceivers. the device is capable of operating in either full-duplex or half -duplex mode in both 10 mbps and 100 mbps operations. operation modes can be selected by har dware configuration pins, software se ttings of management registers, or determined by the on-chip auto negotiation logic. the ADM6993F/fx consists of four major blocks: ? oam engine ? 10/100m phy block ? switch controller block ? built-in 6kx64 ssram 3.1 oam engine an oam packet is used for exchanging the status between tw o end points of a fiber line. an oam packet is not in the ethernet packet format. the ADM6993F/fx supports oa m packets which follow ts-1 000 standard version 1. the oam processor module locates between the mac and fi ber phy. it?s in charge of oam packet transmission and reception. in transmission, it inserts the oam packet in mii traffic, leaving a 96 bit-time gap between packets. if an oam packet insertion request occurs when fiber po rt (port 1) is transmitting an user frame, the oam processor will interrupt the user frame and insert the oam packet. when receiving, the oam processor module can detect the oam packet from mii tra ffic. if the received packet is identi fied as an oam packet, this packet will not be passed to the mac. 3.2 10/100m phy block the 100base-x section of the device im plements the following functional blocks: ? 100base-x physical coding sub-layer (pcs) ? 100base-x physical medium attachment (pma) ? 100base-x physical medium dependent (pmd) the 10base-t section of the device implements the following functional blocks: ? 10base-t physical layer signaling (pls) ? 10base-t physical medium attachment (pma) the 100base-x and 10base-t sections share the following functional blocks: ? clock synthesizer module ? mii registers ? ieee 802.3u auto negotiation the interfaces used for the communication between the phy block and switch core is a mii interface. an auto mdix function is supported. this function can be enabled/disabl ed using the hardware pin. a digital approach for the integrated phy of the ADM6993F/fx has been adopted. data sheet 23 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet function description 3.3 auto negotiation a nd speed configuration 3.3.1 auto negotiation the auto negotiation function provides a mechanism fo r exchanging configuration information between two ends of a link segment and automatically selecting the highes t performance mode of operat ions supported by both devices. fast link pulse (flp) bu rsts provide the signa ling used to communicate auto negotiation abilities between two devices at each end of a link segment. for furt her details regarding auto negotiation, refer to clause 28 of the ieee 802.3u specific ation. the ADM6993F/fx suppor ts four different ethernet protocols, so the inclusion of auto negotiation ensures that the highest perfor mance protocol will be selected ba sed on the ability of the link partner. the auto negotiation function within the ADM6993F/fx can be controlled either by inter nal register access or by the use of configuration pins. if disabled, auto negotiation will not occur until software enab les bit 12 in mii register 0. if auto negotiatio n is enabled, the negotiation process will commence immediately. when auto negotiat ion is enabled, the ADM6993F/fx transmits the abilities programm ed into the aut o negotiation advertisement register at address 04 h via flp bursts. any combination of 10 mbps, 100 mbps, half duplex, and full duplex modes may be selected. auto negotiation cont rols the exchange of config uration information. upon successfully auto negotiating, the abilities reported by the link partner are stored in the auto negotiat ion link partner ability register at address 05 h . the contents of the ?auto negotiation link partner ability re gister? are used to automatically configure the highest performance protocol between the local and far-end nodes. software can determine which mode has been configured by auto negotiation, by comparing the contents of register 04 h and 05 h and then selecting the technology whose bit is set in both registers of highest priority relative to the following list: 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) the basic mode control register at address 0 h controls the enabling, disabling and restarting of the auto negotiation function. when auto negotiati on is disabled, the speed selection bi t (bit 13) controls switching between 10 mbps or 100 mbps operation, while the duplex mode bi t (bit 8) controls switching between full duplex operation and half duplex operation. the speed selection and duple x mode bits have no effect on the mode of operations when the auto negotiation enable bit (bit 12) is set. the basic mode status register at address 1 h indicates the set of available abilitie s for technology types (bit 15 to bit 11), auto negotiation ability (bit 3) , and extended register capab ility (bit 0). these bits ar e hardwired to indicate the full functionality of the ADM6993F/fx. the bmsr also provides status on: ? whether auto negotiation is complete (bit 5) ? whether the link partner is advertising th at a remote fault has occurred (bit 4) ? whether a valid link has been established (bit 2) the auto negotiation advertis ement register at address 4 h indicates the auto negotiati on abilities to be advertised by the ADM6993F/f x. all available abilities are tran smitted by default, but writing to this register or configuring external pins can suppress any ability. the auto negotiation link partner ability register at address 05 h indicates the abilities of the link partner as indicated by auto negotiation communica tion. the contents of this register are considered valid when the auto negotiation complete bit (bit 5, register address 1 h ) is set. 3.3.2 speed configuration the twelve sets of four pins listed in table 12 configure the speed capabilit y of each channel of the ADM6993F/fx. the logic states of these pins are latched into the advertisement register (register address 4 h ) for ADM6993F/fx data sheet function description data sheet 24 rev. 1.21, 2005-11-28 auto negotiation purpose. these pins are also used for evaluating the default value in the base mode control register (register 0 h ) according to table 12 . in order to make these pins with the same read/write priority as software, they should be programmed to 11111111 b in case a user wishes to update the advertisement register through software. 3.4 switch functional description the ADM6993F/fx uses a ?store & forward? switching approach for the following reason: store & forward switches allow switching between diff erent speed media (e.g. 10basex and 100basex). such switches require the large elastic bu ffer especially bridging between a serv er on a 100mbps network and clients on a 10mbps segment. store & forward switches improve overall network performance by acting as a ?network cache? store & forward switches prevent the forwarding of corr upted packets by the frame check sequence (fcs) before forwarding to the destination port. 3.4.1 basic operation the ADM6993F/fx receives incoming packets from one of its ports, searches in the address table for the destination mac address and then forwards the packet to the other port within the same vlan group, if appropriate. if the destination address is not found in th e address table, the ADM6993F/fx treats the packet as a broadcast packet and forwards the packet to th e other ports which are in the same vlan group. table 12 speed configuration advertis e all capabilit y advertis e single capabili ty paralle l detect follow ieee std. auto negoti- ation (pin & eeprom) speed (pin & eeprom ) duplex (pin & eeprom ) auto negot iation advertise capability parallel detect capability 10 0f 10 0h 10 f 10 h 10 0f 10 0h 10 f 10 h 1 0 0 1 x x 1 1 1 1 1 1 0 1 0 1 0 1 1 x x 1 1 1 1 1 0 1 0 1 1 1 0 1 x x 1 1 0 0 0 1 0 0 0 1 1 1 1 x x 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 x 1 1 0 1 0 1 0 1 0 1 0 1 0 1 x 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 x x 1 0 0 1 0 0 0 1 0 0 0 1 x x x 0 1 1 0 1 ? ? ? ? ? ? ? x x x 0 1 0 0 ? 1 ? ? ? ? ? ? x x x 0 0 1 0 ? ? 1 ? ? ? ? ? x x x 0 0 0 0 ? ? ? 1 ? ? ? ? data sheet 25 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet function description the ADM6993F/fx automatically learns the port number of attached network devices by examining the source mac address of all incoming packets at wire speed. if th e source address is not found in the address table, the device adds it to the table. 3.4.2 address learning the ADM6993F/fx uses a hash algorithm to learn the mac address and can learn up to 2k mac addresses. an address is stored in the address table. the ADM6993F/fx searches for the source address (sa) of an incoming packet in the address table and acts as below: if the sa was not found in the address table (a new ad dress), the ADM6993F/fx wait s until the end of the packet (non-error packet) and updates the address table. if the sa was found in the address table, then aging value of each corresponding entry will be reset to 0. when the da is pause command, then the learning proc ess will be disabled auto matically by ADM6993F/fx. 3.4.3 address recognition and packet forwarding the ADM6993F/fx forwards the incoming packets between bridged ports according to the destination address (da) as below. all the packet forwardi ng will check vlan first. a forwarding port must be withi n the same vlan as the source port. 1. if the da is an unicast addres s and the address was fo und in the address tabl e, the ADM6993F/fx will check the port number and acts as follows: a) if the port number is equal to the port on which the packet was received, the packet is discarded. b) if the port number is different, th e packet is forwarded across the bridge. 2. if the da is an unicast address and the address was not found, the ADM6993F/fx treats it as a multicast packet and forwards it across the bridge. 3. if the da is a multicast address, the packet is forwarded across the bridge. 4. if the da is pause command (01- 80-c2-00-00-01), then this pack et will be dropped by ADM6993F/fx. ADM6993F/fx can issue and learn pause command. 5. ADM6993F/fx will forward the packet with da of ( 01-80-c2-00-00-00), filter out the packet with da of (01-80- c2-00-00-01), and forward the packet with da of (0 1-80-c2-00-00-02 ~ 01-80-c2-00-00-0f) decided by eeprom reg.7 h . 3.4.4 address aging address aging is supported for topology changes such as an address moving from one port to the other. when this happens, the ADM6993F/fx internally has a 300 seco nds timer and will aged out (remove) the address from the address table. aging function ca n be enabled/disabled by user. norm ally, disabling aging function is for security purpose. 3.4.5 buffers and queues the ADM6993F/fx incorporates transmitted queues and the receiving buffer area for the three ethernet ports. the receiving buffers as well as the transmitted queues are located within the ADM6993F/fx along with the switch fabric. the buffers are divided into 192 blocks of 256 bytes each. the queues of each port are managed according to each port's read/write pointer. 3.4.6 back off algorithm the ADM6993F/fx implements the truncated exponent ial back off algorithm compliant to the ieee802.3 csma/cd standard. ADM6993F/fx will re start the back off algorithm by choosing 0-9 collision counts. the ADM6993F/fx resets the collis ion counter after 16 consecutive re transmit trials. ADM6993F/fx data sheet function description data sheet 26 rev. 1.21, 2005-11-28 3.4.7 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the typical number is 96-bits time. the value is 9.6 s for 10mbps ethernet, and 960ns for 100mbps fast ethernet. ADM6993F/fx provides the option of a 92-bit gap in eeprom to prevent packet lost when flow control is turned off and clock p.p.m. value differs. 3.4.8 illegal frames the ADM6993F/fx will discard all illegal fr ames such as small packets (less than 64 bytes), oversized packets (greater than 1 518 or 1522 bytes) an d bad crcs. dribbling packing with go od crc value will be accepted by ADM6993F/fx. in case of bypass m ode is enabled, ADM6993F/fx will suppor t tagged packets up to 1522 bytes, and untagged packet with size up to 1518 bytes. in case of non-bypass mode, ADM6993F/fx will support tagged packets up to 1522bytes, and untagged packets up to 1518bytes. 3.4.9 half duplex flow control back pressure function is supported for half-duplex operation. when the ADM6993F/fx cannot allocate a receiving buffer fo r an incoming packet (buffer full), the device will tr ansmit a jam pattern on the port, thus forcing a collision. back pressu re is enabled by the bpen set during reset asserting. an infi neon-admtek co ltd proprietary algorithm is implemented inside the adm69 93f/fx to prevent back pressure function causing hub partitioned under heavy traffic environment and reduce the packet lost rate to increase the whole system performance. 3.4.10 full duplex flow control when full duplex port runs out of its receiving buffer, a pause packet co mmand will be issued by ADM6993F/fx to notice the packet sender to pause the transmission. this fram e based flow control is totally compliant to ieee 802.3x. ADM6993F/fx can issue or receive pause packet. 3.4.11 broadcast storm filter if broadcast storming filter is enable, the broadcast packet s over the rising threshold within 50 ms will be discarded by the threshold setti ng. see eeprom reg.10 h . broadcast storm mode after initial: time interval: 50 ms the max. packet number = 7490 in 100base, 749 in 10base table 13 port rising/falling threshold per port rising threshold 00 01 10 11 all 100tx disable 10% 20% 40% not all 100tx disable 1% 2% 4% per port falling threshold 00 01 10 11 all 100tx disable 5% 10% 20% not all 100tx disable 0.5% 1% 2% data sheet 27 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet function description 3.4.12 auto tp mdix function at normal application which switch conn ects to nic card is by one by one tp cable. if switch connects other devices such as another switch must be by two way. the first one is cross over tp cable. the second way is to use extra rj45 which crosses over internal tx+- and rx+- signals. by the second way customers can use one by one cable to connect two switch devices. all these efforts causes extra costs and are no good solutions. ADM6993F/fx provides auto mdix function which can adju st tx+- and rx+- at correct pin. users can use one by one cable between ADM6993F/fx and ot her devices either switches or nics. 3.5 converter functional description 3.5.1 fault propagation the ADM6993F/fx media converter incorporates a fault prop agation feature, which allows indirect sensing of a fiber link loss via the 10/100base-tx utp connection . whenever the ADM6993F/fx media converter detects a link loss condition on the receive fiber (fiber lnk o ff), it disables its utp link pulse so that a link loss condition will be sensed on t he utp port to which the ADM6993F/fx medi a converter is connected. this link loss can then be sensed and reported by a network management agent in the remote utp port's host equipment. this feature will affect the ad m6993f/fx utp lnk led. the ADM6993F/fx media converter also incorporates a far end fault feature, which allows the stations on both ends of a pairs of fibers to be informed when there is a problem with one of th e fibers. without far end fault, it is impossible for a fiber interface to detect a problem that affects only its transmitting fiber. when far end fault is su pported and e nabled, a loss of received signal (link) will cause th e transmitter to generate a far end fault pattern in order to inform the device at the far end of the fiber pair that a fault has occurred. unless fiber link loss occurred, if the utp port link fail, the ADM6993F/fx media converter will also g enerate a far end fault pattern in order to inform the device at the fa r end of the fiber pair that a fault has occurred. 3.5.2 redundant link the ADM6993F/fx media converter incorporates a redund ant link feature, which allows designing a cost- effective redundant tx fx media converter to provide a more reliable fiber link. at converter mode (fxmode[1:0]=10 and rdnt_en=1), pi n cas_dis of primary ADM6993F/fx connects to pin chip_dis of secondary ADM6993F/fx. ? while fx port works well, pin c as_dis will output "1" to disable 2 nd ADM6993F/fx ? while fx fiber link loss or the remote fault detection happens, pin cas_dis will ou tput ?0? to enable 2 nd ADM6993F/fx. ? while ADM6993F/fx disables, tx port will become hi-z state. table 14 drop scheme for each queue drop scheme for each queue discard mode utilization 00 01 10 11 00 0% 0% 0% 0% 01 0% 0% 25% 50% 11 0% 25% 50% 75% ADM6993F/fx data sheet function description data sheet 28 rev. 1.21, 2005-11-28 3.5.3 loop-back mode the ADM6993F/fx media converter incorporates a loop-bac k mode, which allows users or isp to diagnose the local or the remote network equipment. the loop-back is used to check the operation of the switch and ensure the device's connection on the media side. ? while lpbk_p0=1, the received data fr om port 1/port 2 will be routed thro ugh the receiving path back to the transmitting path on port 0 mii interface (between switch core and embedded port 0 phy). ? while lpbk_p1=1, the received data fr om port 0/port 2 will be routed thro ugh the receiving path back to the transmitting path on port 1 mii interface (between switch core and embedded port 1 phy). ? while lpbk_p2=1, the received data fr om port 0/port 1 will be routed thro ugh the receiving path back to the transmitting path on port 2 mii interface. note: the address learning, packet filter, crc check, le ngth check and loop-back function are not performed in snooping mode. 3.5.4 snooping mode the ADM6993F/fx media converter incorporates a snoop ing mode, which allows packets perform cut-through between tx<-->fx while both tx and fx ports operat e on 100m full mode. on snoo ping mode, the packets will not enter the switch core to perform store and forward mechanisms. ? while snp_en=1, the adm6993 f/fx tx fx media converter will act tx<- ->fx bridge while both tx and fx ports operate on 100m mode. ? while snp_en=0, the adm69 93f/fx tx fx media converter will force all packets to enter the switch core to perform store and forward mechanisms. 3.5.5 fiber_sd led the ADM6993F/fx media converter provides a fiber_sd led on original ldspd[1] pin. fiber_sd is used to indicate the signal status of the fiber port. 3.6 serial management interf ace (smi) register access the smi consists of two pins, management data clock (sdc) and management data input/output (sdio). the ADM6993F/fx is designed to support an sdc frequency up to 25 mhz. the sdio line is bi-directional and may be shared with other devices. the sdio pin requires a 1.5 k ? pull-up which will pull sdio to a logic ?1? state during idle and turn around periods. ADM6993F/fx requires a single initialization sequence of 35 bits of preamble following power-up/hardware reset. the first 35 bits are preamble consisting of 35 contigu ous logic ?1? bits on sdio and 35 corresponding cycles on sdc. following preamble, the start-of-frame field is in dicated by a <01> pattern. the next field signals the operation code (op): <10> indicates read from management register operation, and <01> indicates write to management register operation. the next field is manageme nt register address. it is 10 bits wide and the most significant bit is transferred first. table 15 smi read/write command format operation preamble sfd op chipid[1:0] unused register address ta data read 35?1?s 01 10 2 bits chipid 00 6 bits address z0 32 bits data read write 35?1?s 01 01 2 bits chipid 00 6 bits address 10 32 bits data write data sheet 29 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet function description during read operation, a 2-bit turn around (ta) time s pacing between the register addr ess field and data field is provided for the sdio to avoid contention. following t he turnaround time, a 32-bit data stream is read from or written into the management registers of the ADM6993F/fx. figure 3 smi read operation figure 4 smi write operation 3.6.1 preamble suppression the smi of ADM6993F/fx supports a preamble suppressi on mode. if the station manag ement entity (i.e. mac or other management controller) determines that all device s which are connected to the same sdc/sdio in the system support preamble suppression, then the station management entity needs not to generate preamble for each management transaction. the ADM6993F/fx requires a single initialization sequence of 35 bits of preamble following power-up /hardware reset. this requirement is generally met by pullin g-up the resistor of sdio. while the ADM6993F/fx will respond to management accesses with out preamble, a mi nimum of one idle bit between management transactions is required. when ADM6993F/fx detects th at there is an ad dress matched, then it will enable read/wri te capability for external access. when an addres s is mismatched, then ADM6993F /fx will tri-state the sdio pin. 3.6.2 read eeprom regi ster via smi register the following 2 steps are for reading the data of eeprom register via smi interface. write the address of the desired eeprom regi ster and read command to smi register 04 h ex. <35?1?s><01><01><00000><10011><10>< 000 0000000 000001 0000000000000000 > cmd address data read ADM6993F/fx inter nal eeprom mapping reg.1 h . read smi register 04. the data of desired eeprom register will be in bit [15:0]. ex. <35?1?s><01><10><00000><10011> ADM6993F/fx data sheet function description data sheet 30 rev. 1.21, 2005-11-28 3.6.3 write eeprom regi ster via smi register to write data into desired eeprom register, write the addr ess of the eeprom register. ex. <35?1?s><01><01><00000><00100><10>< 001 0000000 000001 0001000001000000> cmd address data write ADM6993F/fx inter nal eeprom mapping reg.1 h . with value 820f. 3.7 reset operation the ADM6993F/fx can be reset either by hardware or so ftware. a hardware reset is accomplished by applying a negative pulse, with the duration of at least 100 ms to the rc pin of the ADM6993F/fx during normal operation to guarantee internal ssram is reset well. hardware reset operation samples the pins and initializes a ll registers to their default values. this process includes re-evaluation of all hardware configurable registers. a hardware reset affects all embedded phys in the device. software reset can reset all embedded phys and it does not latch the external pins nor reset the registers to their respective default value. this can be achieved by writing ff to eeprom reg.3f h . logic levels on several i/o pins are detected during a hardware reset to determine the initial functionality of ADM6993F/fx. some of these pins are us ed as output ports after reset operation. care must be taken to ensure that the configuration setup will not interf ere with normal operations. dedicated configuration pins can be tied to vcc or ground directly. configuration pins multiple xed with logic level output functions should be either weakly pulled up or weakly pulled down through external resistors. 3.7.1 write eeprom regist er via eeprom interface to write data into desired eeprom register via eeprom interface: if external eeprom 93c46 or 93c66 exists, any writ e programming instructions after ewen instruction is executed can be upd ated effectively on eeprom co ntent and ADM6993F/fx internal mapping register at the same time. if no external eeprom exists, eecs/eeck/eedi must be kept tri-state at least 100ms after hardware reset. any write programming instructions a fter ewen instruction is executed can be updated effectively on ADM6993F/fx internal mapping register. please notice that ADM6993F/fx can only id entify 93c66-programming instructions if no external eeprom. data sheet 31 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description 4 registers description this chapter descri bes eeprom registers. 4.1 eeprom registers table 16 eeprom register map register bit 15-8 bit 7-0 default value 00 h signature 4154 h 01 h port 0 configuration 802f h 02 h port 1 configuration 802f h 03 h port 2 configuration 802f h 04 h tos priority map low vlan priority map low f0f0 h 05 h miscellaneous configuration 0 c0 06 h miscellaneous configuration 1 82e8 h 07 h miscellaneous configuration 2 1480 08 h port 2 to port map port 1 to port map port 0 to port map 777 h 09 h filter control register 1 filter control register 0 0 h 0a h filter control register 3 filter control register 2 0 h 0b h filter control register 5 filter control register 4 0 h 0c h filter control register 7 filter control register 6 0 h 0d h filter control register 9 filter control register 8 0 h 0e h filter control register 11 filter control register 10 0 h 0f h filter control register 13 filter control register 12 0 h 10 h filter control register 15 filter control register 14 0 h 11 h filter type register 0 0 h 12 h filter type register 1 0 h 13 h filter register 0 0 h 14 h filter register 1 0 h 15 h filter register 2 0 h 16 h filter register 3 0 h 17 h filter register 4 0 h 18 h filter register 5 0 h 19 h filter register 6 0 h 1a h filter register 7 0 h 1b h filter register 8 0 h 1c h filter register 9 0 h 1d h filter register 10 0 h 1e h filter register 11 0 h 1f h filter register 12 0 h 20 h filter register 13 0 h 21 h filter register 14 0 h ADM6993F/fx data sheet registers description data sheet 32 rev. 1.21, 2005-11-28 22 h filter register 15 0 h 23 h pvid and pcid mask of port 0 1 h 24 h pvid and pcid mask of port 0 0 h 25 h pvid and pcid mask of port 1 1 h 26 h pvid and pcid mask of port 1 0 h 27 h pvid and pcid mask of port 2 1 h 28 h pvid and pcid mask of port 2 0 h 29 h tag rule 0 f000 h 2a h tag rule 0 00ff h 2b h tag rule 1 f000 h 2c h tag rule 1 00ff h 2d h tag rule 2 f000 h 2e h tag rule 2 00ff h 2f h tag rule 3 f000 h 30 h tag rule 3 00ff h 31 h tag rule 4 f000 h 32 h tag rule 4 00ff h 33 h tag rule 5 f000 h 34 h tag rule 5 00ff h 35 h tag rule 6 f000 h 36 h tag rule 6 00ff h 37 h tag rule 7 f000 h 38 h tag rule 7 00ff h 39 h miscellaneous configuration 2 0000 h 3a h vendor code[15:0] 0000 h 3b h model number [7:0] vendor code [23:16] 0000 h 3c h vendor code[23:8] 0000 h table 16 eeprom register map (cont?d) register bit 15-8 bit 7-0 default value data sheet 33 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description 4.2 eeprom regist er descriptions table 17 registers address spaceregisters address space module base address end address note eeprom ? 0000 h ???? h table 18 registers overview register short name register long name offset address page number sr signature register 00 h 35 pcr_0 port configuration register 0 01 h 35 pcr_1 port configuration register 1 02 h 36 pcr_2 port configuration register 2 03 h 37 vlan_tos_pmr vlan(tos) priority map register 04 h 38 mc_0 miscellaneous configuration 0 05 h 39 mcr_1 miscellaneous configur ation register 1 06 h 40 mcr_2 miscellaneous configur ation register 2 07 h 41 pbvlan_mr port base vlan port map register 08 h 41 pcfc_1_0 packet filter control register 1 and 0 09 h 43 tftr_0 filter type register 0 11 h 44 tftr_1 filter type register 1 12 h 44 fr_0 filter register 0 13 h 45 fr_1 filter register 1 14 h 45 fr_2 filter register 2 15 h 45 fr_3 filter register 3 16 h 45 fr_4 filter register 4 17 h 45 fr_5 filter register 5 18 h 45 fr_6 filter register 6 19 h 45 fr_7 filter register 7 1a h 45 fr_8 filter register 8 1b h 45 fr_9 filter register 9 1c h 45 fr_10 filter register 10 1d h 45 fr_11 filter register 11 1e h 45 fr_12 filter register 12 1f h 45 fr_13 filter register 13 20 h 45 fr_14 filter register 14 21 h 45 fr_15 filter register 15 22 h 45 pb_id_0_0 port base vlan id and mask 0 of port 0 23 h 46 pb_id_1_0 port base vlan id and mask 1 of port 0 24 h 46 pb_id_0_1 port base vlan id and mask 0 of port 1 25 h 47 pb_id_1_1 port base vlan id and mask 1 of port 1 26 h 47 pb_id_0_2 port base vlan id and mask 0 of port 2 27 h 48 pb_id_1_2 port base vlan id and mask 1 of port 2 28 h 48 ADM6993F/fx data sheet registers description data sheet 34 rev. 1.21, 2005-11-28 the register is addressed wordwise. tpr_0_0 tag port rule 0 register 0 29 h 49 tpr_1_0 tag port rule 1 register 0 2a h 49 tpr_0_1 tag port rule 0 register 1 2b h 49 tpr_1_1 tag port rule 1 register 1 2c h 50 tpr_0_2 tag port rule 0 register 2 2d h 49 tpr_1_2 tag port rule 1 register 2 2e h 50 tpr_0_3 tag port rule 0 register 3 2f h 49 tpr_1_3 tag port rule 1 register 3 30 h 50 tpr_0_4 tag port rule 0 register 4 31 h 49 tpr_1_4 tag port rule 1 register 4 32 h 50 tpr_0_5 tag port rule 0 register 5 33 h 49 tpr_1_5 tag port rule 1 register 5 34 h 50 tpr_0_6 tag port rule 0 register 6 35 h 49 tpr_1_6 tag port rule 1 register 6 36 h 50 tpr_0_7 tag port rule 0 register 7 37 h 49 tpr_1_7 tag port rule 1 register 7 38 h 50 mcr_3 miscellaneous configur ation register 3 39 h 50 mcr_4 miscellaneous configuration 4 3a h 52 mcr_5 miscellaneous configur ation register 5 3b h 52 mcr_6 miscellaneous configur ation register 6 3c h 52 table 19 register access types mode symbol description hw description sw read/write rw register is used as input for the hw register is readable and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latches high signal at high level, clear on read sw can read the register latch low, self clearing llsc latches high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latches high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) latch low, mask clearing llmk latches high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) table 18 registers overview (cont?d) register short name register long name offset address page number data sheet 35 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description 4.2.1 eeprom register format signature register port configuration register 0 interrupt high, self clearing ihsc differentiates the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiates the input signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiates the input signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiates the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interr upt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is readable and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be clea red due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is readable and writable by sw. table 20 registers clock domainsregisters clock domains clock short name description sr offset reset value signature register 00 h 4154 h field bits type description signature 15:0 ro signature 4154 h sig , default (at) table 19 register access types (cont?d) mode symbol description hw description sw u r 6 l j q d w x u h ADM6993F/fx data sheet registers description data sheet 36 rev. 1.21, 2005-11-28 port configuration register 1 pcr_0 offset reset value port configuration register 0 01 h 820f h field bits type description bm 15 rw bypass mode(tx packets same as rx) 1 b e , enable ltm 14:10 rw limit total mac 00000 b , disable others b , maximum total mac anpd 9 rw port 0 auto-negotiation para llel detect follow ieee802.3 0 b b , both 1 b h , half only (default) ansc 8 rw port 0 auto-negotiation advertise single capability 0 b e , expand(default) 1 b s , single pbp 7 rw port-base priority pr 6:4 rw priority rule/000 000 b , port base priority 001 b , [tcp,tos,tag] 010 b , [tcp,tag,tos] 011 b , [tag,tcp,tos] 100 b , [tos,tag] 101 b , [tag,tos] dx 3 rw duplex this bit is unused if corresponding po rt is not connected to internal phy 0 b hd , half duplex 1 b fd , full duplex (default) sp 2 rw speed this bit is unused if corresponding po rt is not connected to internal phy 0 b 10m , 10base-t 1 b 100m , 100tx ane 1 rw auto negotiation enable this bit is unused if corresponding po rt is not connected to internal phy 0 b d , disable auto-negotiation 1 b e , enable auto-negotiation. (default) fc 0 rw 802.3x flow control command ability u z % 0 u z / 7 0 u z $ 1 3 ' u z $ 1 6 & u z 3 % 3 u z 3 5 u z ' ; u z 6 3 u z $ 1 ( u z ) & data sheet 37 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description port configuration register 2 pcr_1 offset reset value port configuration register 1 02 h 820f h field bits type description bm 15 rw bypass mode(tx packets same as rx) 1 b e , enable ltm 14:10 rw limit total mac 00000 b , disable others b , maximum total mac anpd 9 rw port 1 auto-negotiation para llel detect follow ieee802.3 0 b b , both 1 b h , half only (default) ansc 8 rw port 1 auto-negotiation advertise single capability 0 b e , expand(default) 1 b s , single pbp 7 rw port-base priority pr 6:4 rw priority rule/000 000 b , port base priority 001 b , [tcp,tos,tag] 010 b , [tcp,tag,tos] 011 b , [tag,tcp,tos] 100 b , [tos,tag] 101 b , [tag,tos] dx 3 rw duplex this bit is unused if corresponding po rt is not connected to internal phy 0 b hd , half duplex 1 b fd , full duplex (default) sp 2 rw speed this bit is unused if corresponding po rt is not connected to internal phy 0 b 10m , 10base-t 1 b 100m , 100tx ane 1 rw auto negotiation enable this bit is unused if corresponding po rt is not connected to internal phy 0 b d , disable auto-negotiation 1 b e , enable auto-negotiation. (default) fc 0 rw 802.3x flow control command ability u z % 0 u z / 7 0 u z $ 1 3 ' u z $ 1 6 & u z 3 % 3 u z 3 5 u z ' ; u z 6 3 u z $ 1 ( u z ) & ADM6993F/fx data sheet registers description data sheet 38 rev. 1.21, 2005-11-28 vlan(tos) priority map register pcr_2 offset reset value port configuration register 2 03 h 820f h field bits type description bm 15 rw bypass mode(tx packets same as rx) 1 b e , enable ltm 14:10 rw limit total mac 00000 b , disable others b , maximum total mac res 9:8 ro reserved pbp 7 rw port-base priority pr 6:4 rw priority rule/000 000 b , port base priority 001 b , [tcp,tos,tag] 010 b , [tcp,tag,tos] 011 b , [tag,tcp,tos] 100 b , [tos,tag] 101 b , [tag,tos] dx 3 rw duplex this bit is unused if corresponding po rt is not connected to internal phy 0 b hd , half duplex 1 b fd , full duplex (default) sp 2 rw speed this bit is unused if corresponding po rt is not connected to internal phy 0 b 10m , 10base-t 1 b 100m , 100tx ane 1 rw auto negotiation enable this bit is unused if corresponding po rt is not connected to internal phy 0 b d , disable auto-negotiation 1 b e , enable auto-negotiation. (default) fc 0 rw 802.3x flow control command ability vlan_tos_pmr offset reset value vlan(tos) priority map register 04 h f0f0 h u z % 0 u z / 7 0 u r 5 h v u z 3 % 3 u z 3 5 u z ' ; u z 6 3 u z $ 1 ( u z ) & data sheet 39 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description note: 0 b : low priority queue. q01 b : high priority queue. q1the weight ratio is 1:n. the default is q0 for un-tagged and none ip frame. miscellaneous configuration 0 field bits type description ip7 15 rw priority of the packet which (is?) the precedence field of ip header is 7 ip6 14 rw priority of the packet which the precedence field of ip header is 6 ip5 13 rw priority of the packet which the precedence field of ip header is 5 ip4 12 rw priority of the packet which the precedence field of ip header is 4 ip3 11 rw priority of the packet which the precedence field of ip header is 3 ip2 10 rw priority of the packet which the precedence field of ip header is 2 ip1 9 rw priority of the packet which the precedence field of ip header is 1 ip0 8 rw priority of the packet which the precedence field of ip header is 0 tag7 7 rw priority of the packet which th e priority field of tag is 7 tag6 6 rw priority of the packet which th e priority field of tag is 6 tag5 5 rw priority of the packet which th e priority field of tag is 5 tag4 4 rw priority of the packet which th e priority field of tag is 4 tag3 3 rw priority of the packet which th e priority field of tag is 3 tag2 2 rw priority of the packet which th e priority field of tag is 2 tag1 1 rw priority of the packet which th e priority field of tag is 1 tag0 0 rw priority of the packet which th e priority field of tag is 0 mc_0 offset reset value miscellaneous configuration 0 05 h c0 h field bits type description dm 15:12 rw discard mode (drop scheme for each queue) u z , 3 u z , 3 u z , 3 u z , 3 u z , 3 u z , 3 u z , 3 u z , 3 u z 7 $ * u z 7 $ * u z 7 $ * u z 7 $ * u z 7 $ * u z 7 $ * u z 7 $ * u z 7 $ * u z ' 0 u z 9 / $ 1 u z 3 / u z 3 4 5 u r 5 h v u z , 3 * u r 5 h v u z % 6 ( u z % 6 7 ADM6993F/fx data sheet registers description data sheet 40 rev. 1.21, 2005-11-28 miscellaneous configuration register 1 vlan 11 rw enable replace vlan id 0 &1 by pvid checking of the length of crs 1 b , enable pl 10 rw packet length 0 b , 1536 1 b , 1518 pqr 9:8 rw priority queue ratio 00 b , 1:2 01 b , 1:4 10 b , 1:8 11 b , 1:16 res 7:6 ro reserved ipg 5 rw ipg leveling 0 b , 96bt(default) 1 b , 92bt res 4:3 ro reserved bse 2 rw broadcast storming enable 1 b e , enable bst 1:0 rw broadcast storming threshold[1:0] mcr_1 offset reset value miscellaneous configuration register 1 06 h 82e8 h field bits type description res 15:11 ro reserved et 10 rw enable tenlmt 1 b , enable limit traffic to 10m cdp 9 rw check the destination port is in the same vlan group 1 b , enable efm 8 rw emulated force mode for port0 0 b d , disable(default) 1 b e , enable res 7:3 ro reserved dffe 2 rw disfefi(disable far end fault/0) dp 1 rw discard packet after 16th collision 0 b d , doesn?t discard field bits type description u r 5 h v u z ( 7 u z & ' 3 u z ( ) 0 u r 5 h v u z ' ) ) ( u z ' 3 u z $ ' data sheet 41 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description miscellaneous configuration register2 packet filtering mode:00 b : forward,01 b : discard,10 b : forward the packet to cpu port(defined in bit [7:6] of register 0x07). if this packet is re ceived from cpu port, th is packet will be forwarde d to the vlan group.11 b : forward the packet to cpu port. if this packet is received from cpu port, this packet will be discarded. port base vlan port map register ad 0 rw aging disable 0 b e , enable aging mcr_2 offset reset value miscellaneous configuration register 2 07 h 1480 h field bits type description pfm1 15:14 rw packet filtering mode for received da= 01 80 c2 00 00 10 ~ 01 80 c2 00 00 ff pfm2 13:12 rw packet filtering mode for received da= 01 80 c2 00 00 02 ~ 01 80 c2 00 00 0f pfm3 11:10 rw packet filtering mode for received da= 01 80 c2 00 00 01 and opcode!= pause pfm4 9:8 rw packet filtering mode for received da= 01 80 c2 00 00 00 cpn 7:6 rw cpu port number res 5:0 ro reserved pbvlan_mr offset reset value port base vlan port map register 08 h 777 h field bits type description u z 3 ) 0 u z 3 ) 0 u z 3 ) 0 u z 3 ) 0 u z & 3 1 u r 5 h v u z / ( ' u z , 6 u z 0 & ) u z / 3 u z / ( ' / u z 3 0 u z 2 $ 0 u z 3 0 u z 7 ) u z 3 0 ADM6993F/fx data sheet registers description data sheet 42 rev. 1.21, 2005-11-28 field bits type description led 15 rw put off leds of utp port 0 b , always puts off leds of utp po rt when utp link down (is linked down or links down?) 1 b , leds of utp port show dipsw setting when auto-negotiation (is?) disable(d?) and link(ed?) down is 14 rw idiot setting 0 b , disable idiot setting, sumo will send dipsw setting to co when utp port auto-negotiation (is?) enable(d) and link(ed?) down 1 b , enable idiot setting, sumo will always send 10mh to co when utp port auto-negotiation enable and link down mcf 13 rw mc failure 0 b , asserts mc_failure when load eeprom fails 1 b , doesn?t assert mc_failure when load eepom fails lp 12 rw link partner 0 b , if auto-negotiation is enabled, follows speed and duplex setting to negotiate with link partner. 1 b , if auto-negotiation is enabled, always advertises full capability to its link partner. ledl 11 rw put off leds of utp port 0 b , puts off leds of utp port du ring loopback test . (default) 1 b , doesn?t put off leds of utp port during loopback test. pm2 10:8 rw port 2 to port map oam 7 rw transmit oam frame 0 b , transmitts one oam frame if stat e changes or state notification request frame is received. (default) 1 b , transmitts three oam frames if st ate changes or state notification request frame is received. pm1 6:4 rw port 1 to port map tf 3 rw transmitting frame 0 b , stops transmitting frame if pause frame received. (default) 1 b , doesn?t stop transmitting frame if pause frame received when flow control capability is disabled. pm0 2:0 rw port 0 to port map data sheet 43 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description packet filter control registers 1 and 0 op code bit[4:3]00 b : priority. priority is defi ned in op code bit[2:0] ;01 b : discard. op code bi t[2:0] is reserved and should keep always 0;1x b : reserved. pcfc_1_0 offset reset value packet filter control register 1 and 0 09 h 0000 h field bits type description apr2 15 rw apply to port 2 rx 0 b dna , do not apply 1 b apl , apply apr1 14 rw apply to port 1 rx 0 b dna , do not apply 1 b apl , apply apr0 13 rw apply to port 0 rx 0 b dna , do not apply 1 b apl , apply op14 12:8 rw op code for filter defined in register 14 h (16 h , 18 h , 1a h , 1c h , 1e h , 20 h , 22 h ) apr2 7 rw apply to port 2 rx 0 b dna , do not apply 1 b apl , apply apr1 6 rw apply to port 1 rx 0 b dna , do not apply 1 b apl , apply apr0 5 rw apply to port 0 rx 0 b dna , do not apply 1 b apl , apply op13 4:0 rw op code for filter which is defined in register 13 h (15 h , 17 h , 19 h , 1b h , 1d h , 1f h , 21 h ) u z $ 3 5 u z $ 3 5 u z $ 3 5 u z 2 3 u z $ 3 5 u z $ 3 5 u z $ 3 5 u z 2 3 ADM6993F/fx data sheet registers description data sheet 44 rev. 1.21, 2005-11-28 filter type register 0 00 b : tcp/udp port number;01 b : ip protocol id;10 b : ethernet type;11 b : reserved filter type register 1 tftr_0 offset reset value filter type register 0 11 h 0000 h field bits type description tf_7 15:14 rw type of filter 7 tf_6 13:12 rw type of filter 6 tf_5 11:10 rw type of filter 5 tf_4 9:8 rw type of filter 4 tf_3 7:6 rw type of filter 3 tf_2 5:4 rw type of filter 2 tf_1 3:2 rw type of filter 1 tf_0 1:0 rw type of filter 0 tftr_1 offset reset value filter type register 1 12 h 0000 h field bits type description tf_15 15:14 rw type of filter 15 tf_14 13:12 rw type of filter 14 tf_13 11:10 rw type of filter 13 tf_12 9:8 rw type of filter 12 tf_11 7:6 rw type of filter 11 tf_10 5:4 rw type of filter 10 u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b u z 7 ) b data sheet 45 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description 00 b : tcp/udp port number;01 b : ip protocol id;10 b : ethernet type;11 b : reserved filter register 0 other filter registers have the same structure and characteristics as filter register 0 ; the offset addresses are listed in table 21 . tf_9 3:2 rw type of filter 9 tf_8 1:0 rw type of filter 8 fr_0 offset reset value filter register 0 13 h 0000 h field bits type description filter 15:0 rw filter table 21 other filter regsiters register short name register long name offset address page number fr_1 filter register 1 14 h fr_2 filter register 2 15 h fr_3 filter register 3 16 h fr_4 filter register 4 17 h fr_5 filter register 5 18 h fr_6 filter register 6 19 h fr_7 filter register 7 1a h fr_8 filter register 8 1b h fr_9 filter register 9 1c h fr_10 filter register 10 1d h fr_11 filter register 11 1e h fr_12 filter register 12 1f h fr_13 filter register 13 20 h fr_14 filter register 14 21 h fr_15 filter register 15 22 h field bits type description u z ) l o w h u ADM6993F/fx data sheet registers description data sheet 46 rev. 1.21, 2005-11-28 port base vlan id and mask 0 of port 0 port base vlan id and mask 1 of port 0 if (tag packet) then tag = {tagin[15:12], ((tagin[11 :0] & ~mask) | (pvid & mask))} if (untag packet) then tag = {pkt_prt[2:0], 0 b , pvid} pb_id_0_0 offset reset value port base vlan id and mask 0 of port 0 23 h 0001 h field bits type description dpri 15:12 rw pvid mask[3:0] default priority pvid 11:0 rw pvid port base vlan id pb_id_1_0 offset reset value port base vlan id and mask 1 of port 0 24 h 0000 h field bits type description led 9 rw turn on all led at the same time during led self test 0 b , disable (default) 1 b , enable epc 8 rw enable polarity checking by using idle pulse 0 b , disable (default) 1 b , enable pvid 7:0 rw pvid mask[11:4] u z ' 3 5 , u z 3 9 , ' 5 h v u z / ( ' u z ( 3 & u z 3 9 , ' data sheet 47 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description port base vlan id and mask 0 of port 1 port base vlan id and mask 1 of port 1 if (tag packet) then tag = {tagin[15:12], ((tagin[11 :0] & ~mask) | (pvid & mask))} if (untag packet) then tag = {pkt_prt[2:0], 0 b , pvid} pb_id_0_1 offset reset value port base vlan id and mask 0 of port 1 25 h 0001 h field bits type description dpri 15:12 rw pvid mask[3:0] default priority pvid 11:0 rw pvid port base vlan id pb_id_1_1 offset reset value port base vlan id and mask 1 of port 1 26 h 0000 h field bits type description pvid 7:0 rw pvid mask[11:4] u z ' 3 5 , u z 3 9 , ' 5 h v u z 3 9 , ' ADM6993F/fx data sheet registers description data sheet 48 rev. 1.21, 2005-11-28 port base vlan id and mask 0 of port 2 port base vlan id and mask 1 of port 2 if (tag packet) then tag = {tagin[15:12], ((tagin[11 :0] & ~mask) | (pvid & mask))} if (untag packet) then tag = {pkt_prt[2:0], 0 b , pvid} pb_id_0_2 offset reset value port base vlan id and mask 0 of port 2 27 h 0001 h field bits type description dpri 15:12 rw pvid mask[3:0] default priority pvid 11:0 rw pvid port base vlan id pb_id_1_2 offset reset value port base vlan id and mask 1 of port 2 28 h 0000 h field bits type description pvid 7:0 rw pvid mask[11:4] u z ' 3 5 , u z 3 9 , ' 5 h v u z 3 9 , ' data sheet 49 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description tag port rule 0 register 0 other tag port rule 0 registers have the same structure and characteristics as tag port rule 0 register 0 ; the offset addresses are listed in table 22 . tag port rule 1 register 0 tpr_0_0 offset reset value tag port rule 0 register 0 29 h f000 h field bits type description res 15:0 ro reserved table 22 other tag port rule 0 registers register short name register long name offset address page number tpr_0_1 tag port rule 0 register 1 2b h tpr_0_2 tag port rule 0 register 2 2d h tpr_0_3 tag port rule 0 register 3 2f h tpr_0_4 tag port rule 0 register 4 31 h tpr_0_5 tag port rule 0 register 5 33 h tpr_0_6 tag port rule 0 register 6 35 h tpr_0_7 tag port rule 0 register 7 37 h tpr_1_0 offset reset value tag port rule 1 register 0 2a h 00ff h field bits type description res 11:9 ro reserved u r 5 h v 5 h v u r 5 h v 5 h v ADM6993F/fx data sheet registers description data sheet 50 rev. 1.21, 2005-11-28 other tag port rule 1 registers have the same structure and characteristics as tag port rule 1 register 0 ; the offset addresses are listed in table 23 . miscellaneous configuration register 3 table 23 other tag port rule 1 regsiters register short name register long name offset address page number tpr_1_1 tag port rule 1 register 1 2c h tpr_1_2 tag port rule 1 register 2 2e h tpr_1_3 tag port rule 1 register 3 30 h tpr_1_4 tag port rule 1 register 4 32 h tpr_1_5 tag port rule 1 register 5 34 h tpr_1_6 tag port rule 1 register 6 36 h tpr_1_7 tag port rule 1 register 7 38 h mcr_3 offset reset value miscellaneous configuration register 3 39 h 0000 h field bits type description oam 15 rw s7-s8 and s9 of oam frame show phy status disable 0 b , s7-s8 and s9 of oam frame show phy status if phy link(s?) up. (default) 1 b , s7-s8 and s9 of oam frame don't show phy status if phy link up. le 14 rw link enable 0 b , link disable during loop back test(default) 1 b , link enable during loop back test res 13 ro reserved rl 12 rw redundant link 0 b , enable redundant link in converter mode(default) 1 b , disable redundant link fp 11 rw fault propagation 0 b , enable fault propagation in converter mode(default) 1 b , disable fault propagation 100s 10 rw 100m snooping 0 b , enable 100m snooping in converter mode(default) 1 b , disable snooping u z 2 $ 0 u z / ( u r 5 h v u z 5 / u z ) 3 u z 6 u z $ 3 b 3 u r 5 h v u z 3 1 b 9 u z 7 $ * data sheet 51 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet registers description ap_p 9:7 rw all packet/pppoe 0 b , all packets 1 b , pppoe only res 6:4 ro reserved pn_v 3 rw port number/vlan id base grouping 0 b , port number base grouping(default) 1 b , received vlan id base grouping tag 2:0 rw vlan tag 0 b , recognizes vlan tag automatically(default) 1 b , disable field bits type description ADM6993F/fx data sheet registers description data sheet 52 rev. 1.21, 2005-11-28 miscellaneous configuration register 4 miscellaneous configuration register 5 miscellaneous configuration register 6 mcr_4 offset reset value miscellaneous configuration 4 3a h 0000 h field bits type description vid 15:0 rw vender id bit[15:0] mcr_5 offset reset value miscellaneous configuration register 5 3b h 0000 h field bits type description mn 15:8 rw model number bit[7:0] vid 7:0 rw vender id bit[23:16] mcr_6 offset reset value miscellaneous configuration register 6 3c h 0000 h field bits type description mn 15:0 rw model number bit[23:8] u z 9 , ' u z 0 1 u z 9 , ' u z 0 1 data sheet 53 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet electrical specification 5 electrical specification dc and ac. 5.1 dc characterization 5.2 ac characterization power on reset timing, eeprom interface timing, 10ba se-tx mii timing, 100base-tx mii timing, reduce mii timing, gpsi(7-wire) timing, and smi timing. table 24 electrical absolute maximum rating parameter symbol values unit note / test condition min. typ. max. power supply v cc -0.3 2.7 v input voltage v in -0.3 v cc + 0.3 v output voltage vout -0.3 v cc + 0.3 v storage temperature tstg -55 155 c power dissipation pd 990 mw esd rating esd 2 kv table 25 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. power supply 1) 1) vcc3o. vccbias vcc 3.135 3.3 3.465 v input voltage vin 0 - vcc v junction operating temperature tj 0 25 115 c table 26 dc electrical characteristics for 3.3 v operation 1) 1) under vcc = 3.0 v~ 3.6 v, tj = c ~ 115 c parameter symbol values unit note / test condition min. typ. max. input low voltage vil 0.8 v ttl input high voltage vih 2.0 v ttl output low voltage vol 0.4 v ttl output high voltage voh 2.4 v ttl input pull_up/down resistance ri 50 k ? vil = 0 v or vih = vcc ADM6993F/fx data sheet electrical specification data sheet 54 rev. 1.21, 2005-11-28 power on reset timing figure 5 power on reset timing eeprom interface timing figure 6 eeprom interface timing table 27 power on reset timing parameter symbol values unit note / test condition min. typ. max. rst low period t rst 100 ms ttl start of idle pulse width t conf 100 ns ttl table 28 eeprom interface timing parameter symbol values unit note / test condition min. typ. max. eesk period t esk 5120 ns eesk low period t eskl 2550 2570 ns eesk high period t eskh 2550 2570 ns eedi to eesk rising setup time t erds 10 ns tconf trst trst 0us 50us 100us 150us rst * a ll configuration pin s terdh terds tewdd tesk tesk teskl teskl teskh teskh 0us 10us 20us 30us eecs eesk eedo eedi data sheet 55 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet electrical specification 10base-tx mii input timing 10base-tx input timing conditions figure 7 10base-tx mii input timing 10base-tx mii output timing 10base-tx mii output timing conditions eedi to eesk rising hold time t erdh 10 ns eesk falling to eedo output delay time t ewdd 20 ns table 29 10base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period tck 400 ns mii_rxclk low period tckl 160 240 ns mii_rxclk high period tckh 160 240 ns mii_crs rising to mii_rxdv rising tcsva 0 10 ns mii_rxclk rising to mii_rxd, mii_rxdv, mii_crs output delay trxod 200 ns table 28 eeprom interface timing (cont?d) parameter symbol values unit note / test condition min. typ. max. tcsva trxod tck tc k l tc k l tck h tck tck h 0ns 1000ns 2000ns mii_rxclk mii_rxdv mii_rxd mii_crs ADM6993F/fx data sheet electrical specification data sheet 56 rev. 1.21, 2005-11-28 figure 8 10base-tx mii output timing 100base-tx mii input timing 100base tx mii inpu t timing conditions figure 9 100base-tx mii input timing table 30 10base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period tck 400 ns mii_txclk low period tckl 160 240 ns mii_txclk high period tckh 160 240 ns mii_txd, mii_txen to mii_txclk rising setup time ttxs 10 ns mii_txd, mii_txen to mii_txclk rising hold time ttxh 10 ns tthx ttxs tck tckl tckl tckh tck tckh 0ns 500ns 1000ns 1500ns 2000ns 2500 n mii_txclk mii_txen mii_txd tcsva trxod tckl tck tckl tckh tckh tck 0ns 100ns 200ns mii_rxclk mii_rxdv mii_rxd mii_crs data sheet 57 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet electrical specification 100base-tx mii output timing 100base-tx mii outp ut timing conditions figure 10 100base-tx mii output timing reduce mii timing reduce mii timing conditions table 31 100base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period tck 40 ns mii_rxclk low period tckl 16 24 ns mii_rxclk high period tckh 16 24 ns mii_crs rising to mii_rxdv rising tcsva 0 10 ns mii_rxclk rising to mii_rxd, mii_rxdv, mii_crs output delay trxod 20 30 ns table 32 100base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period tck 40 ns mii_txclk low period tckl 16 24 ns mii_txclk high period tckh 16 24 ns mii_txd, mii_txen to mii_txclk rising setup time ttxs 10 ns mii_txd, mii_txen to mii_txclk rising hold time ttxh 10 ns ttxh ttxs tckl tck tckl tckh tckh tck 0ns 50ns 100ns 150ns 200ns 250ns mii_txclk mii_txen mii_txd ADM6993F/fx data sheet electrical specification data sheet 58 rev. 1.21, 2005-11-28 figure 11 reduce mii timing gpsi (7-wire) input timing gpsi (7-wire) input timing conditions table 33 100base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. rmii_refclk period tck 20 ns rmii_refclk low period tckl 10 ns rmii_refclk high period tckh 10 ns txen, txd to refclk rising setup time ttxs 4 ns txe, txd to refclk rising hold time ttxh 2 ns csrdv, rxd to refclk rising setup time trxs 4 ns crsdv, rxd to refclk rising hold time trxh 2 ns ttxh ttxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_t xen txd[1:0] trxh trxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_crsdv rxd[1:0] data sheet 59 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet electrical specification figure 12 gpsi (7-wire) input timing gpsi (7-wire) output timing gpsi (7-wire) output timing conditions figure 13 gpsi (7-wire) output timing table 34 gpsi (7-wire) input timing parameter symbol values unit note / test condition min. typ. max. gpsi_rxclk period tck 100 ns gpsi_rxclk low period tckl 40 60 ns gpsi_rxclk high period tckh 40 60 ns gpsi_rxclk rising to gpsi_crs/gpsi_col output delay tod 50 70 ns tod tck tckl tckl tckh tck tckh 0ns 250ns 500ns gpsi_rxclk gpsi_rxd gpsi_crs/col ttxh ttxs tck tckl tckl tckh tck tckh 0ns 250ns 500ns gpsi_txclk gpsi_txd gpsi_txen ADM6993F/fx data sheet electrical specification data sheet 60 rev. 1.21, 2005-11-28 smi timing figure 14 smi timing table 35 gpsi (7-wire) output timing parameter symbol values unit note / test condition min. typ. max. gpsi_txclk period tck 100 ns gpsi_txclk low period tckl 40 60 ns gpsi_ t xclk high period tckh 40 60 ns gpsi_txd, gpsi_txen to gpsi_txclk rising setup time ttxs 10 ns gpsi_txd, gpsi_txen to gpsi_txclk rising hold time ttxh 10 ns table 36 smi timing parameter symbol values unit note / test condition min. typ. max. sdc period t ck 20 ns sdc low period t ckl 10 ns sdc high period t ckh 10 ns sdio to sdc rising setup time on read/write cycle t sds 4 ns sdio to sdc rising hold time on read/write cycle t sdh 2 ns tsdh tsds tsdc tsdcl tsdcl tsdch tsdc tsdch 0ns 25ns 50ns 75ns 100ns sdc sdio data sheet 61 rev. 1.21, 2005-11-28 ADM6993F/fx data sheet packaging 6 packaging 128 pqfp packaging for ADM6993F/fx figure 15 128 pqfp packaging for ADM6993F/fx 18.5 mm 20.0 +/- 0.1 mm 23.2 +/- 0.2 mm 3.4 mm max 12.5 mm 14.0 +/- 0.1 mm 17.2 +/- 0.2 mm 0.5 mm published by infineon technologies ag www.infineon.com |
Price & Availability of ADM6993F
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |